The present invention relates to timing analysis for electronic circuits, for example, very large-scale integrated (VSLI) circuits.
Before a circuit design is finalized for fabrication, timing analysis tools are used to verify the proper timing of the circuit. The clock or clocks for the circuit must trigger the various circuit components are proper times. The timing and I/O characteristics of the various basic circuit components, including resistors, transistors and wiring, are known, so that timing diagrams may be created by a circuit designer for very small circuits to ensure that timing is proper.
However, such timing diagrams are impractical for all but the smallest circuits. Thus software tools have been developed to aid circuit designers. These timing analysis tools may be classified as one of two types: static or dynamic. In dynamic timing analysis, the proposed circuit to be created is modeled at the transistor level, and the software, by solving matrix-based equations, determines the timing of the circuit for a test vector. One of the best-known dynamic timing analysis programs is SPICE, developed at the University of California, Berkeley.
Dynamic timing analysis programs that model each transistor have a high level of accuracy, permitting the designer to accurately verify the circuit timing before fabrication. However, for large circuits, dynamic timing analysis is not practical, because the computational power required to process a test vector through the transistor-level model becomes very large.
In response to the computational limitations of dynamic timing analysis programs, static timing analysis (STA) programs have been developed. Although the creation of STA blocks can be time consuming, once they are created, the blocks may be reused for modeling other circuits. Blocks having a known functionality may be used to design large integrated circuits. A library of blocks thus exists that is available to circuit designers, and each of the blocks has known I/O timing characteristics in terms of their interface pins. When the circuit is to be fabricated, an actual transistor-level design is substituted for the block.
The use of STA blocks permits fast and frequent timing checks, even for designs with many millions gates, since timing at the transistor level can be avoided.
However, STA blocks provide only interface timing for a certain clock waveform, for example that a certain block has a minimum time delay and a maximum time delay for a rising edge arriving at a pin 1 of the block and exiting at pin 20 for a certain clock waveform. There is no support for clocks generated within the circuit, and the blocks are often not very accurate, since the worst and best case scenarios may diverge widely.
In response to the limitations of these so-called black-box models, gray box models have been developed that describe the interface timing in terms of a combination of interface pins and internal points within the circuit. These gray box models also lose accuracy compared with dynamic timing analysis and have long characterization times. Moreover, there is no way to apply original constraints to the design when using the gray box model, since the logic of the model is not preserved and thus there is no way to place constraints on the logic into the model.
Clock characterization has also been used to improve the black box model, by providing additional constraints on the clock waveforms provided to the circuit. However, this approach has similar disadvantages to the gray-box models.
A background of timing analysis tools can be found in Dunlap, Evans and Rigge, “Managing Complexity in IC Design—Past Present and Future,” Bell Labs Technical Journal, Autumn 1997.
The publication of January 2001 entitled “Hierarchical Static Timing Analysis Using Interface Logic Models” discusses the use of interface logic models which model a circuit based on interface logic.